Periodic signals are used in a variety of electronic devices. One type of periodic signals are clock signals that can be used to establish the timing of a signal or the timing at which an operation is performed on a signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock signal. More specifically, read data signals are typically coupled from a memory device in synchronism with a read data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The write data strobe signal should have a phase that is the quadrature (having a phase 90-degrees relative to the phase) of the write data signals so that a transition of the write data strobe signal occurs during a “data eye” occurring at the center of the period in which the write data signals are valid.
Internal clock signals generated in electronic devices, for example, memory devices or memory controllers, are often synchronized or have some other controlled phase relationships relative to external or internal clock signals. For example, with reference to a memory device, a quadrature clock signal used for latching write data and outputting read data may be generated in the memory device to which the data are being written. The quadrature clock signal is typically generated in the memory device from an internal clock signal that is also derived from the system clock signal.
Internal clock signals having synchronized or some other controlled phase relationships with external and internal clock signals may also be used for applications other than for use as a write data and outputting read data strobe signal. For example, a “frequency doubler” circuit, which generates an output clock signal having twice the frequency of an input clock signal, can be implemented using an appropriate logic circuit that receives the input clock signal and quadrature versions of the input clock signal. Internal clock signals may also be generated having other than a quadrature phase relationships. Generally, any phase relationship between output clock signals can be used.
Various techniques can be used to generate a quadrature clock signal or read/write data strobe signal. If the frequency of the internal clock signal is fixed, quadrature clock signals can be generated by a timing circuit that simply generates a transition of the quadrature clock signals a fixed time after a corresponding transition of the internal clock signal. However, synchronous memory devices are typically designed and sold to be operated over a wide range of clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate quadrature signals from the internal clock signal. Instead, a circuit that can adapt itself to an internal clock signal having a range of frequencies must be used.
An example of such a circuit is a multi-phase clock signal generator. A multi-phase clock signal generator, as known, generates multi-phase clock signals to provide several clock signals having fixed phase relationships to a reference clock signal, such as an external or internal clock signal. In operation, a multi-phase clock signal generator should be initialized to ensure the generated clock signals have the correct phase relationship. A conventional method of initializing a multi-phase clock signal generator will now be described with reference to FIG. 1. The conventional multi-phase clock signal generator 100 includes a delay line 105 having a plurality of delay elements 110a-d coupled in series with each other. Each of the delay elements 110a-d has two inputs, two outputs, and a control input (not shown). Each delay element 110a-d has two inputs and two outputs to provide for a double-ended configuration where both a clock signal 120 and its complement 121 are received and processed. A single-ended configuration may also be used.
Each of the delay elements 110a-d couples a signal from its input to its output with a delay corresponding to a delay control signal applied to its control input. The input of the initial delay element 110a receives a clock signal 120 and its complement 121. The outputs of all but the last delay element 110d is coupled to the input of the subsequent delay element. The output of each delay element 110a-d forms a respective tap of the delay line 105 to provide four clock signals C90, C180, C270, and C360, respectively, C360 is a one clock delayed version of C0 at lock status. As indicated by their names, the C90 signal has a 90 degree phase difference with the input clock signal 120. The C180 signal has a 180 degree phase difference with the input clock signal 120, the C270 signal a 270 degree phase difference, and the C360 signal a 360 degree phase difference. As explained in greater detail below, the amount of voltage-controlled delay provided by each of the delay elements 110a-d sets a minimum and maximum amount of delay that can be achieved by the delay line 105.
To ensure the proper phase relationships are maintained correctly during operation between the four provided clock signals, a two-step locking phase detector 130 receives the input clock signal 120, the C180 signal and the C360 signal. The phase detector 130 will first lock the inversion of C180 signal to the C0 signal, and then in the second step, lock the C360 signal with the C0 signal. To lock the C0 and C180 signal, the phase detector 130 produces an error signal corresponding to a mismatch between the falling edge of the C180 signal and the rising edge of the C0 signal. The error signal is used to adjust the delay of the delay elements 110a-d such that the C0 and C180 signals are 180 degrees apart. As shown in FIG. 1, the error signal is converted to a control signal by a control signal generator, such as charge-pump and loop filter 140. The control signal is used by a bias voltage generator 150 to couple a VBIAS signal to the control inputs of the delay elements 110a-d. In the second step of operation of the phase detector 130, an error signal is generated corresponding to a mismatch between a rising edge of the C0 signal and a rising edge of the C360 signal. In a similar manner, the error signal is used to adjust the delay of the delay elements 110a-d. This two-step locking process may be sufficient in some cases where the duty cycle or slow locking time is not an issue. However, difficulties occur when the incoming clock signal contains some duty cycle distortion, as will now be explained with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating signals from FIG. 1. A clock period is shown in FIG. 2 as tCK, between t0 and t2. The incoming clock signal, C0 has an amount of duty cycle distortion shown by tDCD. That is, in the case where the C0 signal had an ideal, 50 percent duty cycle, the high pulse would extend from time t0 to time t1 in FIG. 2. However, as shown, the C0 high pulse is significantly shorter. The phase detector 130 then locks the falling edge of the C180 signal with the rising edge of the C0 signal at time t2, as shown by arrow 210. The phase detector 130 will lock the signals within a tolerance, shown by ±tPDmin in FIG. 2. Due to the duty cycle distortion, the rising edge of the C180 signal is tx1 off from time t1, where the signal should be for a 180 degree phase difference. Accordingly, the C180 signal has been delayed tx1 too much. Recall that adjusting the control voltage applied to the delay elements 105 of FIG. 1 adjusts the delay of all the delay elements 110a-d. The C360 signal will now be 2*tx1 off from locked with C0, as shown in FIG. 2. The second step of operation of the phase detector 130 will be to adjust the delay of the delay elements 110a-d such that the C360 signal is synchronized with the C0 signal, by matching the rising edge of the C0 signal with the rising edge of the C360 signal, as shown in the second timing diagram of FIG. 2 by the arrow 220.
Duty cycle distortion in incoming clock signals is not uncommon, and, taking signal jitter into consideration, could be a significant portion of reference clock period. With duty cycle distortion, the two-step locking phase detector 130 may cease to function properly. The delay line 105 may have insufficient range to accommodate the lengthy tx1 and 2*tx1 delay times that should be compensated for according to FIG. 2. One solution to this problem is to place a duty-cycle control element prior to and in series with the multi-phase clock signal generator 100. This may ensure the multi-phase clock signal generator receives a clock signal with a correct duty cycle. However, a duty cycle control element also has a limited working range and takes much longer time to achieve corrected output signals. Accordingly, this solution may also become impractical as speeds increase and timing requirements tighten.
There is accordingly a need for an improved system and method for providing multi-phase clock signals.